1. Technical Field
The present invention is directed generally to integrated circuit technology. More specifically, the present invention is directed to a method of transparently reducing power consumed by a high-speed communication link.
2. Description of Related Art
With the advent of fast processors, data-intensive applications (e.g., multimedia, graphics) and network architectures such as wide area networks etc., there has been an increasing demand for high data bandwidth in the computer industry. One method that has been used to meet that demand is to transfer data in parallel to obtain a higher aggregate bandwidth. Basically, the data is broken down into packets and the packets are routed to a multiplicity of communication link transmitters. The transmitters then transfer the packets of data to corresponding communication link receivers. Once received, the data is serialized and processed.
Due to the recent emergence of systems-on-a-chip (SOC) products, it is inevitable that the communication links would be embedded in chips. In an SOC, all the electronics of a computer system, for example, or large portions of packet switch systems are integrated onto a single chip. Generally, the SOCs are implemented using complementary metal oxide semiconductor (CMOS) technology. CMOS transistors are constantly decreasing in size, leading to ever-faster transistors and higher degrees of integration. Indeed, some 0.1 micron CMOS circuits may contain thousands of transistors and operate in the GHz range. In addition, CMOS circuits can operate at very low voltages. Hence, CMOS technology is ideal for implementing these communication links on a chip. Note that the communication links will henceforth be referred to as high-speed communication links to stress the fact that they operate in the GHz range.
As is well known in the art, the more digital logic that is integrated in a chip, the more power the chip consumes. And, since only a limited amount of heat generated by a chip can be dissipated through the chip package, the chip has to be designed such that its performance is maximized while its power consumption is minimized.
Consequently, what is needed is a method of reducing communication link power consumption and thus the power consumption of the SOC within which the link is embedded. In doing so, however, the link""s performance characteristics should be maintained while costly over-design of the link is avoided.
The present invention provides a method of reducing power consumption while maintaining performance characteristics and avoiding costly over-design of a high-speed communication link embedded in an SOC. The method includes synthesizing the communication link at a reduced voltage to determine and isolate circuitry that is supply-voltage-critical from circuitry that is non-supply-voltage-critical. The supply-voltage-critical circuitry contains components that may not operate at the reduced voltage without degrading the performance characteristics of the communication link. A non-reduced voltage is used to drive the supply-voltage-critical circuitry while the reduced voltage is used to drive the non-supply-voltage-critical circuitry. The reduced voltage is generated using a voltage regulator embedded in the communication link.
In one embodiment, the two circuitries interface each other at a boundary that is selected to yield the minimal amount of interfacing points. This optimizes the communication link since a level shifter has to be used at each interfacing point to change the voltage level of migrating signals.
Further, the SOC may contain hundreds of high-speed communication links. Each communication link has an embedded voltage regulator. Consequently, the area of the SOC used by the regulators may be substantial. To minimize this area, a plurality of the high-speed communication links may be designed to share a common voltage regulator.